In a conventional architecture of a processor, the processor can receive one or more instructions in a processing cycle, from a storage location such as an instruction cache or main memory. In each processing cycle, the processor can execute one or more instructions in parallel in one or more execution units. Bit flips or errors can occur in any instruction of the one or more instructions, in any of the stages or components involved in the instruction's lifecycle, such as storage, transfer, execution, etc. of the instruction.
For example, the storage locations such as caches or main memory can be implemented using technology such as static random access memory (SRAM), double data rate (DDR) memory, etc., which may be prone to errors. Bit flips can also be introduced in the various network buses and wires involved in transferring the instruction from the storage locations to the processor's execution units. Furthermore, the execution units may also contribute to logic errors while operating on the instruction.
Adding error checks in each stage of the instruction's lifecycle may be expensive and in some cases, impractical. For example, adding parity information to each cache line of an instruction cache or each storage location in main memory/DDR may be expensive, and even if errors in the storage locations can be detected (and in some cases, corrected), bit flips may be introduced downstream in the processing of the instruction. Furthermore, it may not be possible to add error checking mechanisms for each of the buses which transport the instruction, or for each execution unit which operates on the instruction. Therefore, pinpointing the source of an error may be difficult, and if the errors are left unchecked, the errors can result in various exceptions or system faults.
Accordingly, there is a corresponding need for effective error checking mechanisms which can provide an end-to-end solution for errors introduced in any stage of an instruction's lifecycle and in any component storage locations or transport between storage locations for the instruction.